1. Field
The present invention relates to processes for producing electrical interconnects, and, more particularly, processes for producing high performance transmission lines and interconnects between integrated circuits, discrete devices, and passive components in highly integrated three-dimensional structures.
2. Description of Related Art
Increasingly complex electronic systems require increasingly denser structures of integrated circuits, passive components, and other discrete elements. Typical two-dimensional structures, where the elements are laid out on a printed circuit board or similar structure, no longer meet the size, weight, and performance requirements of advanced electronic systems. Hence, three-dimensional structures are being used to provide the needed levels of electronic circuit integration. These three-dimensional structures generally comprise multiple layers of devices along with multiple layers of interconnects to provide electrical connections between the devices.
One approach for providing interconnects in a multiple layer structure is that used in high-density multilayer interconnect (HDMI) techniques. J. L. Licari and D. J. Smith in U.S. Pat. No. 5,485,038, issued Jan. 16, 1996, describe an HDMI structure using alternating conductor metallization and insulating layers. Licari, et al. disclose dielectric layers formed by curtain coating of ultraviolet photoimageable epoxy material and conductor layers formed on the dielectric layers by thin film printing, sputtering or plating. Vertical interconnects (vias) are formed through the dielectric layers to interconnect the metallization pattern on adjacent conductor layers.
The conventional polyimide materials used for RF packaging are not photoimageable. Thus, the metallization patterns and interlayer vias must be formed by photolithography, which typically involves applying, imaging, developing and removing a photoresist layer for each metallization and dielectric layer. Many process steps are thereby required for each layer. Plasma etching using photoresist is generally used to form the interconnect structures.
Plasma etching methods are limited in their ability to produce complex structures and are also restricted by practical considerations in the vertical depth of the features (a few microns). The depth restriction is due to the low etch rates of most plasma etching schemes for etching polymers (<3000 Å/min) and the lack of robust material masking. Complex structures such as via holes with tapered sidewalls, terraced structures or asymmetrically shaped features are also difficult to produce using plasma etching. Some laboratories have reported forming via holes in polyimide polymer films with sloped sidewalls. The method employed uses tapered erosion masks to obtain sloped etch features, but is limited in the range of sidewall angles and the depth of the etched features. Producing asymmetric structures (i.e., different sidewall profiles) is beyond the capability of current plasma etching technology.
S. Y. Chou in U.S. Pat. No. 5,772,905, “Nanoimprint Lithography,” issued Jun. 30, 1998, describes a process for molding structures in thermoplastic polymer film to create ultra-fine structures on or in a substrate. Chou discloses a nanoimprint process that presses a mold into the polymer film to form holes and trenches with high aspect ratios in structures less than 25 nanometers. The mold may consist of a thick layer of silicon dioxide on a silicon substrate and is patterned using electron beam lithography, reactive ion etching (RIE), and other methods. To form the vias and trenches, the mold is pressed into polymethylmethacrylate (PMMA) film spun on a silicon wafer. RIE is used to remove PMMA residue from the bottom of the molded via and trench regions. The vias and trenches are then metalized by using an evaporation technique. Alternatively, the molded and etched film may be used as a mask to support the formation of recesses in the substrate by an etching process. The recesses in the substrate can then be used to support further processing steps.
The techniques disclosed by Chou address the creation of two-dimensional ultra-fine structures on or in a substrate. However, there exists a need in the art for the creation of three-dimensional structures in multiple layers at or above a substrate. There also exists a need in the art for creating interconnection structures in dielectric materials to provide for connections between layers in a multiple layer structure using a minimum number of steps for the process. Furthermore, there exists a need in the art for a process that provides for the creation of complex interconnection structures such as tapered sidewalls, terraced structures, or asymmetrically shaped features in multiple layer structures.